(1) Field of the Invention
The present invention relates to interconnect structures in a semiconductor device and a method for making the same, and more particularly to interconnect structures on electrodes or resistor elements of a semiconductor device formed by a compound semiconductor of gallium arsenide (GaAs) and a method for making such interconnect structures.
(2) Description of the Related Art
Conventionally, an N-type semiconductor layer with ionic impurities being implanted is used as resistor elements of a semiconductor integrated circuit device constituted by a semiconductor of compounds such as GaAs. However, the N-type semiconductor layer has problems in its linearity as a resistor element and stability for high frequencies. Thus, in order to replace this, a thin film such as that of tungsten silicon nitride (WSiN) is used as a resistor element. Also, for the gate electrode of a field effect transistor of GaAs, the tungsten silicon (WSi) which has a high heat resistance is generally used.
The conventional steps of forming interconnects on a thin film resistor element and electrodes are explained with reference to FIGS. 1A through 1D showing the process steps involved.
First, as shown in FIG. 1A, a film of silicon dioxide SiO.sub.2 which is a protective film 5 is deposited over an entire surface of a substrate wherein an active layer 1 and electrodes 2 and 3 are formed. Next, as shown in FIG. 1B, on the resultant surface, a film of tungsten silicon nitride (WSiN) is deposited by a sputtering process and a resistor element 6 is then formed by a patterning and a dry etching process. Then, as shown in FIG. 1C, a film of SiO.sub.2 is again deposited and flattened and, thereafter, contact holes 7a, 7b are opened on each of the electrodes 2, 3 and the resistor element 6, respectively, by selectively removing the SiO.sub.2 on the respective contact regions. Finally, as shown in FIG. 1D, the interconnects 9 are formed through the contact holes 7a, 7b by using Ti/Pt/Au and Au metal plating.
In the above described conventional technique of forming interconnects on a resistor element of WSiN, the contact hole is formed by a dry etching process using usually a CF.sub.4 gas. However, as can be appreciated from the graph of FIG. 2 which shows etching rates for dry etching performed using CF.sub.4 gas with respect to various metals, no problem will be caused by any slight over-etching when a contact hole is to be formed on an electrode of Au. However, in the case where a contact hole is to be formed on resistor elements or electrodes of WSiN or WSi, there will be an over-etching problem since there is only small difference in the etching rate between the SiO.sub.2 and the WSiN or WSi. Further, in the conventional interconnect structure described above, since the level of electrodes 2, 3 of WSi is below that of the resistor element 6 of WSiN, if the contact holes on both of them are formed simultaneously, the resistor element of WSiN will be etched through by the over-etching. These are problems to be solved by the present invention, in the conventional technique for forming interconnects in the semiconductor device.